HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 240

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 5 Memory Management Unit (MMU)
5.3.3
The results of address comparison determine whether a specific virtual page number is registered
in the TLB. The virtual page number of the virtual address that accesses external memory is
compared to the virtual page number of the indexed TLB entry. The ASID within the PTEH is
compared to the ASID of the indexed TLB entry. All four ways are searched simultaneously. If
the compared values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered.
It is necessary to have software ensure that TLB hits do not occur simultaneously in more than one
way, as hardware operation is not guaranteed if this occurs. An example of setting which causes
TLB hits to occur simultaneously in more than one way is described below. It is necessary to
ensure that this kind of setting is not made by software.
1. If there are two identical TLB entries with the same VPN and a setting is made such that a
2. If several entries which have different ASID with the same VPN are registered in single virtual
3. There is the possibility of simultaneous TLB hits in more than one way. These hits may occur
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REJ09B0269-0100
TLB hit is made only by a process with ASID = H'FF when one is in the shared state (SH = 1)
and the other in the non-shared state (SH = 0), then if the ASID in PTEH is set to H'FF, there is
a possibility of simultaneous TLB hits in both these ways.
memory mode, there is the possibility of simultaneous TLB hits in more than one way when
accessing the corresponding page in privileged mode. Several entries with the same VPN must
not be registered in single virtual memory mode.
depending on the contents of ASID in PTEH when a page to which SH is set 1 is registered in
the TLB in index mode (MMUCR.IX = 1). Therefore a page to which SH is set 1 must not be
TLB Address Comparison
31
0
Virtual Address
31
VPN(31-17)
Index
17
VPN(11-10)
Address Array
Figure 5.9 TLB Indexing (IX = 0)
16
12
11
ASID(7-0)
0
V
Way 0 to 3
PPN(28-10) PR(1-0) SZ C
Data Array
D SH