HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 642

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Serial I/O with FIFO (SIOF)
17.3.6
SICTR is used to set the SIOF operating state. SICTR is initialized by a power-on reset or
software reset.
Rev. 1.00 Dec. 27, 2005 Page 598 of 932
REJ09B0269-0100
Bit
15
14
13 to 10
9
SIOF Control Register (SICTR)
Bit Name
SCKE
FSE
—
TXE
Initial
Value
0
0
All 0
0
R/W
R/W
R/W
R
R/W
Description
Serial Clock Output Enable
This bit is valid in master mode. If this bit is set to 1, the
SIOF initializes the baud rate generator and initiates the
operation. At the same time, the SIOF outputs the clock
generated in the baud rate generator to the SCK_SIO pin.
0: Disables the SCK_SIO output (outputs 0)
1: Enables the SCK_SIO output
Frame Synchronous Signal Output Enable
This bit is valid in master mode. If this bit is set to 1, the
SIOF initializes the frame counter and initiates the
operation.
0: Disables the SIOFSYNC output (outputs 0)
1: Enables the SIOFSYNC output
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmission Enable
This bit setting becomes valid at the start of the next frame
(at the rising edge of the SIOFSYNC signal) and when
valid data is stored in the transmit FIFO. When the 1
setting for this bit becomes valid, the SIOF issues a
transmission transfer request according to the setting of
the TFWM bit in SIFCTR. When transmit data is stored in
the transmit FIFO, transmission of data from the TXD_SIO
pin begins. This bit is initialized by a transmit reset.
0: Disables data transmission from TXD_SIO (outputs 1)
1: Enables data transmission from TXD_SIO