HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 422
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 422 of 980
- Download datasheet (6Mb)
Section 12 Bus State Controller (BSC)
12.4.4
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
Rev. 1.00 Dec. 27, 2005 Page 378 of 932
REJ09B0269-0100
Bit
31 to
21
20
19
18
17
16
15, 14
13
Bit Name
A2ROW1
A2ROW0
A2COL1
A2COL0
DEEP
SDRAM Control Register (SDCR)
Initial
Value
All 0
0
0
0
0
0
All 0
0
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Bits of Row Address for Area 2
Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
Reserved
This bit is always read as 0. The write value should always
be 0.
Number of Bits of Column Address for Area 2
Specify the number of bits of column address for area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
Reserved
These bits are always read as 0. The write value should
always be 0.
Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RMODE bit is
set to 1 while this bit is set to 1, the deep power-down entry
command is issued and the low-power SDRAM enters the
deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
Description
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