HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 315

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 9.2
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
9.2.7
BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data
specified by BDRB.
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
Bus Selection in
BBRB
L bus
I bus
X bus
Y bus
Bit
31 to 0
2.
3.
2.
3.
Break Data Mask Register B (BDMRB)
Bit Name
BDMB31 to
BDMB 0
When the byte size is selected as a break condition, the same byte data must be set in
bits 15 to 8 and 7 to 0 in BDRB as the break data.
Set the data in bits 31 to 16 when including the value of the data bus as an L-bus
break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or
MOVS.W @As+Ix,Ds instruction.
When the byte size is selected as a break condition, the same byte data must be set in
bits 15 to 8 and 7 to 0 in BDRB as the break mask data in BDMRB.
Set the mask data in bits 31 to 16 when including the value of the data bus as an L-
bus break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W
@As+,Ds, or MOVS.W @As+Ix,Ds instruction.
Specifying Break Data Register
BDB31 to BDB16
XDB15 to XDB0
Don’t care
Initial
Value
All 0
R/W
R/W
Description
Break Data Mask B
Specifies bits masked in the break data of channel B
specified by BDRB (BDB31 to BDB0).
0: Break data BDBn of channel B is included in the
1: Break data BDBn of channel B is masked and is not
Note: n = 31 to 0
break condition
included in the break condition
LDB31 to LDB0
IDB31 to IDB0
BDB15 to BDB0
Don’t care
YDB15 to YDB0
Rev. 1.00 Dec. 27, 2005 Page 271 of 932
Section 9 User Break Controller
REJ09B0269-0100