HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 614
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 614 of 980
- Download datasheet (6Mb)
Section 16 Serial Communication Interface with FIFO (SCIF)
In serial reception, the SCIF operates as described below.
1. The SCIF monitors the communication line, and if a 0 start bit is detected, performs internal
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
Note: Reception continues when a receive error (a framing error or parity error) occurs.
4. If the RIE bit in SCSCR is set to 1 when the RDF flag or DR flag changes to 1, a receive-
Figure 16.8 shows an example of the operation for reception in asynchronous mode.
Rev. 1.00 Dec. 27, 2005 Page 570 of 932
REJ09B0269-0100
synchronization and starts reception.
After receiving these bits, the SCIF carries out the following checks.
A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
B. The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR.
C. Overrun error check: The SCIF checks that the ORER flag is cleared to 0 and an overrun
D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
If all the above checks are passed, the receive data is stored in SCFRDR.
FIFO-data-full interrupt (RXI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK flag or ORER flag changes to 1,
a break reception interrupt (BRI) request is generated.
the first is checked.
error does not occur.
set.
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