HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 355
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 355 of 980
- Download datasheet (6Mb)
11.1
The oscillator consists of a clock pulse generator (CPG) block and a watchdog timer (WDT)
block.
The CPG generates clocks supplied to this LSI and controls the power-down modes.
The WDT is a single-channel timer that counts the clock settling time and is used when clearing
standby mode and temporary standbys, such as frequency changes. It can also be used as an
ordinary watchdog timer or interval timer.
11.1.1
The CPG has the following features:
• Seven clock modes: Selection of seven clock modes according to the frequency range to be
• Three clocks generated independently: An internal clock (Iφ) for the CPU and cache; a
• Frequency change function: Internal and peripheral clock frequencies can be changed
• Power-down mode control: The clock can be stopped for sleep mode and standby mode and
The WDT has the following features:
• Can be used to ensure the clock settling time:
• Can switch between watchdog timer mode and interval timer mode.
• Generates internal resets in watchdog timer mode:
frequency is changed.
used and direct connection of crystal resonator or external clock input.
peripheral clock (Pφ) for the peripheral modules; and a bus clock (Bφ = CKIO) for the external
bus interface.
independently using the PLL circuit and divider circuit within the CPG. Frequencies are
changed by software using frequency control register (FRQCR) settings.
specific modules can be stopped using the module standby function.
Use the WDT to cancel standby mode and the temporary standbys which occur when the clock
Internal resets occur after counter overflow.
Selection of power-on reset or manual reset.
Overview
Features
Section 11 On-Chip Oscillation Circuits
Rev. 1.00 Dec. 27, 2005 Page 311 of 932
Section 11 On-Chip Oscillation Circuits
REJ09B0269-0100
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