HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 640

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Serial I/O with FIFO (SIOF)
17.3.5
SICDAR is used to specify the position of the control data in a frame. SICDAR can be specified
only when the FL3 to FL0 bits in SIMDR are specified as 1xxx. SICDAR is initialized by a
power-on reset or software reset.
Rev. 1.00 Dec. 27, 2005 Page 596 of 932
REJ09B0269-0100
Bit
11
10
9
8
7
6 to 4
3
2
1
0
Bit
15
14 to 12
Serial Control Data Assign Register (SICDAR)
Bit Name
RDLA3
RDLA2
RDLA1
RDLA0
RDRE
—
RDRA3
RDRA2
RDRA1
RDRA0
Bit Name
CD0E
—
Initial
Value
0
0
0
0
0
All 0
0
0
0
0
Initial
Value
0
All 0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Description
Control Channel 0 Data Enable
0: Disables transmission and reception of control channel
1: Enables transmission and reception of control channel
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
Receive Left Channel Data Assigns 3 to 0
Specify the position of left-channel data in a receive
frame as B′0000 to B′1110. Receive data for the left
channel is stored in bits SIRDL15 to SIRDL0 in SIRDR.
Note: If the RDLA3 to RDLA0 bits are set to B′1111,
Receive Right Channel Data Enable
0: Disables right channel data reception
1: Enables right channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive Right Channel Data Assigns 3 to 0
Specify the position of right-channel data in a receive
frame as B′0000 to B′1110. Receive data for the right
channel is stored in bits SIRDR15 to SIRDR0 in SIRDR.
Note: If the RDRA3 to RDRA0 bits are set to B′1111,
0 data
0 data
operation is not guaranteed.
operation is not guaranteed.