HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 318

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 User Break Controller
9.2.9
BRCR sets the following conditions:
1. Channels A and B are used in two independent channel conditions or under the sequential
2. A break is set before or after instruction execution.
3. Specify whether to include the number of execution times on channel B in comparison
4. Determine whether to include data bus on channel B in comparison conditions.
5. Enable PC trace.
6. Enable ASID check.
BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for
setting a variety of break conditions.
Rev. 1.00 Dec. 27, 2005 Page 274 of 932
REJ09B0269-0100
Bit
31 to 22
21
20
condition.
conditions.
Break Control Register (BRCR)
Bit Name

BASMA
BASMB
Initial
Value
All 0
0
0
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Break ASID Mask A
Specifies whether bits in channel A break ASID7 to
ASID0 (BASA7 to BASA0) which are set in BASRA are
masked or not.
0: All BASRA bits are included in the break conditions
1: All BASRA bits are not included in the break
Break ASID Mask B
Specifies whether bits in channel B break ASID7 to
ASID0 (BASB7 to BASB0) which are set in BASRB are
masked or not.
0: All BASRB bits are included in the break conditions
1: All BASRB bits are not included in the break conditions
and the ASID is checked
conditions and the ASID is not checked
and the ASID is checked
and the ASID is not checked