HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 671

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Transmission/Reception Reset: The SIOF can separately reset the transmission and reception
units by setting the following bits to 1.
• Transmission reset: TXRST bit in SICTR
• Reception reset: RXRST bit in SICTR
No.
5
2
4
6
1
3
in SIRDR synchronously with SIOFSYNC
Store receive data from RXD_SIO
Set RXE bit in SICTR register to 1
SIRDAR, SICDAR, and SIFCTR
Set SIMDR, SISCR, SITDAR,
Clear RXE bit in SICTR to 0
Figure 17.12 Example of Reception Operation in Slave Mode
Read SIRDR
Time Chart
RDREQ=1?
Transfer
ended?
Start
End
Yes
Yes
No
No
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and the upper limit value of FIFO
request
Set to enable reception
Read receive data
Set to disable reception
SIOF Settings
Rev. 1.00 Dec. 27, 2005 Page 627 of 932
Section 17 Serial I/O with FIFO (SIOF)
Submit reception request
according to the limit
value of receive FIFO
Enable reception when the
frame synchronous signal is
input
Reception
End reception
SIOF Operation
REJ09B0269-0100