HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 599
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 599 of 980
- Download datasheet (6Mb)
Bit
7
6
5
4
3
Bit Name
RTRG1
RTRG0
TTRG1
TTRG0
MCE
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Section 16 Serial Communication Interface with FIFO (SCIF)
Description
Receive FIFO Data Number Trigger 1 and 0
Set the number of receive data bytes that sets the
RDF flag in SCFSR.
The RDF flag is set when the number of receive data
bytes in SCFRDR is equal to or greater than the
trigger set number shown in below.
Asynchronous mode
00: 1
01: 4
10: 8
11: 14
Transmit FIFO Data Number Trigger 1 and 0
Set the number of remaining transmit data bytes that
sets the TDFE flag in SCFSR.
The TDFE flag is set when, as the result of a transmit
operation, the number of transmit data bytes in
SCFTDR is equal to or below the trigger set number
shown in below.
00: 8 (8)
01: 4 (12)
10: 2 (14)
11: 0 (16)
Note: The values in parentheses are the number of
Modem Control Enable
Enables modem control signals CTS and RTS. This
bit is valid only in asynchronous mode.
0: Modem signal disabled*
1: Modem signal enabled
Note: * CTS is fixed at active 0 regardless of the input
empty bytes in SCFTDR when the flag is set.
value, and RTS is also fixed at 0.
Rev. 1.00 Dec. 27, 2005 Page 555 of 932
Clock synchronous mode
00: 1
01: 2
10: 8
11: 14
REJ09B0269-0100
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