HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 674
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HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 17 Serial I/O with FIFO (SIOF)
Table 17.12 Setting Condition of Transmit/Receive Interrupt Flag
Processing when Errors Occur: On occurrence of each of the errors indicated as a status in
SISTR, the SIOF performs the following operations.
• Transmit FIFO underrun (TFUDR)
• Transmit FIFO overrun (TFOVR)
• Receive FIFO overrun (RFOVR)
• Receive FIFO underrun (RFUDR)
• Frame synchronization error (FSERR)
17.4.9
Examples of the SIOF serial transmission and reception are shown in figure 17.13 through figure
17.19.
8-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for
transmit and receive data, frame length = 8 bits
Rev. 1.00 Dec. 27, 2005 Page 630 of 932
REJ09B0269-0100
Transmit interrupt flag
Receive interrupt flag
The immediately preceding transmit data is again transmitted.
The contents of the transmit FIFO are protected, and the write operation causing the overrun is
ignored.
Data causing the overrun is discarded and lost.
The latest read data is output on the bus (undefined value as specification).
The internal counter is reset according to the FSYN signal in which an error occurs.
Transmission and Reception Timing
Setting Condition
TDREQ bit in SISTR is set to 1
RDREQ bit in SISTR is set to 1
Reset Condition
TDREQ bit in SISTR is cleared to 0
Acknowledge from DMAC
RDREQ bit in SISTR is cleared to 0
Acknowledge from DMAC
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