HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 816
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 816 of 980
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Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(2)
If an error occurs during reception in the case of a multi-buffer frame where a receive frame is
divided for storage in multiple buffers, the E-DMAC performs the processing shown in figure
19.7.
In the figure, the invalid receive descriptors (with the RACT bit cleared to 0) represent the normal
reception of data to be stored in buffers, and the valid receive descriptors (with the RACT bit set
to 1) represent unreceived buffers. If a frame receive error occurs with a descriptor shown in the
figure, the status is written back to the corresponding descriptor.
If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register
(EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame
receive request, reception is continued from the buffer after that in which the error occurred.
Rev. 1.00 Dec. 27, 2005 Page 772 of 932
REJ09B0269-0100
E-DMAC
Receive Processing in Case of Multi-Buffer Frame
Inactivates RACT and writes RFE, RFS
Descriptor read
.
.
.
.
.
.
.
.
Figure 19.7 E-DMAC Operation after Receive Error
R
A
C
T
0
0
0
1
1
1
1
1
1
R
D
E
L
0
0
0
0
0
0
0
0
1
Descritptors
R
P
F
1
1
0
0
0
0
0
0
0
0
R
P
F
0
0
0
0
0
0
0
0
0
0
Continue
Continue
Frame
type
Start
Buffer length set
by descriptor
Start of frame
New frame reception
continues from this buffer
Receive error
occurrence
Received data
Unreceived data
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