HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 804

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(b) Transmit Descriptor 1 (TD1)
TD1 indicates the data length of the transmit buffer used by the corresponding descriptor.
The user should set TD1 before the start of a read by the E-DMAC.
(c)
TD2 indicates the start address of the corresponding 32-bit width transmit buffer. An address
value on a longword boundary should be specified.
The user should set TD2 before the start of a read by the E-DMAC.
(2)
Figure 19.3 shows the relationship between a receive descriptor and receive buffer.
The data of a receive descriptor consists of RD0, RD1, RD2, and padding data in groups of 32 bits
from top to end. The length of padding data is determined according to the descriptor length
specified by the DL0 and DL1 bits in EDMR. In the figure, RBA (bits 31 to 0 in RD2) indicates
the start address of a receive buffer. RBL (bits 31 to 16 in RD1) indicates the usable data length of
the receive buffer. RDL (bits 15 to 0 in RD1) indicates the data length of a received frame.
RD0 indicates whether the receive descriptor is valid or invalid as well as information about
descriptor configuration and status. RD1 indicates the length (storage destination size) of data in
the receive buffer to be received according to the specification of the descriptor. RD2 indicates the
start address of the receive buffer for storing receive data.
Depending on the descriptor specification, one receive descriptor can specify the storing of all
receive data of one frame in a receive buffer (single-frame/single-buffer) or multiple descriptors
can specify the storing of the receive data of one frame in receive buffers (single-frame/multi-
buffer). As an example of single-frame/multi-buffer operation, suppose that a row of multiple
descriptors (descriptor list) is prepared, RBL of each descriptor is 500 bytes, and a 1514-byte
Rev. 1.00 Dec. 27, 2005 Page 760 of 932
REJ09B0269-0100
Bit
31 to 16
15 to 0
Transmit Descriptor 2 (TD2)
Receive Descriptor
Bit Name
TDL

Initial
Value
All 0
All 0
R/W
R/W
R
Description
Transmit Buffer Data Length (in bytes)
Indicate the data length of the corresponding transmit
buffer in bytes.
Reserved
These bits are always read as 0. The write value
should always be 0.