HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 27

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 20 Pin Function Controller (PFC).........................................................779
20.1 Overview............................................................................................................................ 779
20.2 Register Configuration....................................................................................................... 780
20.3 Register Descriptions ......................................................................................................... 781
Section 21 I/O Ports ...........................................................................................787
21.1 Overview............................................................................................................................ 787
21.2 Register Descriptions ......................................................................................................... 787
Section 22 User Debugging Interface (H-UDI) .................................................791
22.1 Features.............................................................................................................................. 791
22.2 Input/Output Pins ............................................................................................................... 792
22.3 Register Descriptions ......................................................................................................... 793
22.4 Operation ........................................................................................................................... 802
22.5 Boundary Scan ................................................................................................................... 805
22.6 Usage Notes ....................................................................................................................... 806
22.7 Advanced User Debugger (AUD)...................................................................................... 806
Section 23 List of Registers ...............................................................................807
23.1
23.2 Register Bits....................................................................................................................... 821
20.3.1 Port A Control Register (PACR) .......................................................................... 781
20.3.2 Port B Control Register (PBCR)........................................................................... 782
20.3.3 Port C Control Register (PCCR)........................................................................... 783
20.3.4 Ethernet Controller Pin Control Register (PETCR).............................................. 784
21.2.1 Port A Data Register (PADR)............................................................................... 787
21.2.2 Port B Data Register (PBDR) ............................................................................... 788
21.2.3 Port C Data Register (PCDR) ............................................................................... 790
22.3.1 Bypass Register (SDBPR) .................................................................................... 793
22.3.2 Instruction Register (SDIR) .................................................................................. 793
22.3.3 Boundary Scan Register (SDBSR) ....................................................................... 794
22.3.4 ID Register (SDID)............................................................................................... 801
22.4.1 TAP Controller ..................................................................................................... 802
22.4.2 Reset Configuration .............................................................................................. 803
22.4.3 TDO Output Timing ............................................................................................. 803
22.4.4 H-UDI Reset ......................................................................................................... 804
22.4.5 H-UDI Interrupt .................................................................................................... 804
22.5.1 Supported Instructions .......................................................................................... 805
22.5.2 Points for Attention............................................................................................... 806
Register Addresses
section numbers) ................................................................................................................ 808
(by functional module, in order of the corresponding
Rev. 1.00 Dec. 27, 2005 Page xxv of xlii