ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 989

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

39.7.12
Name:
Address:
Access:
For additional Information, see
• EPT_ENABL: Endpoint Enable
0 = no effect.
1 = enable endpoint according to the device configuration.
• AUTO_VALID: Packet Auto-Valid Enable
0 = no effect.
1 = enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.
• INTDIS_DMA: Interrupts Disable DMA
0 = no effect.
1 = If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.
• NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
0 = no effect.
1 = forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.
• DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
0 = no effect.
1 = enable DATAx Interrupt.
• MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
0 = no effect.
1 = enable MDATA Interrupt.
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
SHRT_PCKT
MDATA_RX
NAK_OUT
31
23
15
–
7
UDPHS Endpoint Control Enable Register
UDPHS_EPTCTLENBx [x=0..6]
0x400A4104 [0], 0x400A4124 [1], 0x400A4144 [2], 0x400A4164 [3], 0x400A4184 [4], 0x400A41A4 [5],
0x400A41C4 [6]
Write-only
ERR_FLUSH
DATAX_RX
NAK_IN/
30
22
14
–
–
6
“UDPHS Endpoint Control Register” on page
ERR_CRISO/
ERR_NBTRA
STALL_SNT/
29
21
13
–
–
5
–
ERR_FL_ISO
RX_SETUP/
NYET_DIS
28
20
12
–
–
4
TX_PK_RDY/
ERR_TRANS
INTDIS_DMA
27
19
11
–
–
3
993.
BUSY_BANK
TX_COMPLT
26
18
10
–
2
–
AUTO_VALID
RX_BK_RDY
SAM3U Series
SAM3U Series
25
17
–
–
9
1
ERR_OVFLW
EPT_ENABL
24
16
–
–
8
0
989
989