ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 891

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

38.6.5.5
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Changing the Comparison Value and the Comparison Configuration
It is possible to change the comparison values and the comparison configurations while the
channel 0 is enabled (see
To prevent unexpected comparison match, the user must use the
Update Register”
PWM_CMPMUPDx) to change respectively the comparison values and the comparison configu-
rations while the channel 0 is still enabled. These registers hold the new values until the end of
the comparison update period (when CUPRCNT is equal to CUPR in
Register”
the next period.
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be fol-
lowed by a write of the register PWM_CMPMUPDx.
Note:
Figure 38-18. Synchronized Update of Comparison Values and Configurations
If the update registers PWM_CMPVUPDx and PWM_CMPMUPDx are written several times
between two updates, only the last written value are taken into account.
End of channel0 PWM period and
end of Comparison Update Period and
and PWM_CMPMx written
End of channel0 PWM period and
end of Comparison Update Period
(PWM_CMPMx) and the end of the current PWM period, then update the values for
and the
“PWM Comparison x Mode Update Register”
Section 38.6.3 ”PWM Comparison
PWM_CMPVUPDx Value
Comparison Value
for comparison x
PWM_CMPVx
User's Writing
Units”).
PWM_CMPMUPDx Value
Comparison configuration
“PWM Comparison x Value
for comparison x
SAM3U Series
SAM3U Series
“PWM Comparison x Mode
User's Writing
PWM_CMPMx
(PWM_CMPVUPDx and
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