ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 1061

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 41-4. GOVRE and OVREx Flag Behavior
6430D–ATARM–25-Mar-11
(ADC12B_CHSR)
(ADC12B_CHSR)
ADC12B_LCDR
ADC12B_CDR0
ADC12B_CDR1
(ADC12B_SR)
(ADC12B_SR)
(ADC12B_SR)
(ADC12B_SR)
(ADC12B_SR)
GOVRE
OVRE0
Trigger
DRDY
EOC0
EOC1
CH0
CH1
If the ADC12B_CDR is not read before further incoming data is converted, the corresponding
Overrun Error (OVRE) flag is set in the Status Register (ADC12B_SR).
Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error)
in ADC12B_SR.
The OVRE and GOVRE flags are automatically cleared when ADC12B_SR is read.
Undefined Data
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and
then reenabled during a conversion, its associated data and its corresponding EOC and OVRE
flags in ADC12B_SR are unpredictable.
The ADC12B can be triggered externally by software or internally from the Timer Counter or
PWM.
Undefined Data
Conversion
Undefined Data
Conversion
Data CH0
Data CH0
Data CH1
Conversion
Data CH1
SAM3U Series
Data CH0
Read ADC12B_CDR1
Data CH0
Read ADC12B_CDR0
Read ADC12B_SR
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