ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 962

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 39-13. Data OUT Transfer for an Endpoint with Two Banks
39.6.8.13
Figure 39-14. Bank Management, Example of Three Transactions per Microframe
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USB Bus
Packets
Virtual RX_BK_RDY
Bank 0
Virtual RX_BK_RDY
Bank 1
RX_BK_RDY = (virtual bank 0 | virtual bank 1)
(UDPHS_EPTSTAx)
FIFO (DPR)
Bank 0
FIFO (DPR)
Bank 1
USB bus
Transactions
Microcontroller FIFO
(DPR) Access
SAM3U Series
SAM3U Series
t = 0
High Bandwidth Isochronous Endpoint OUT
Host sends first data payload
Token OUT
Set by Hardware,
Data payload written
in FIFO endpoint bank 0
MDATA0
RX_BK_RDY
Write by UDPHS Device
USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192
Mb/s (24 MB/s): 3x1024 data bytes per microframe.
To support such a rate, two or three banks may be used to buffer the three consecutive data
packets. The microcontroller (or the DMA) should be able to empty the banks very rapidly (at
least 24 MB/s on average).
NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe.
If NB_TRANS > 1 then it is High Bandwidth.
MDATA1
Data OUT 1
Data OUT 1
Read Bank 1
DATA2
ACK
Read by Microcontroller
Set by Hardware
Data Payload written
in FIFO endpoint bank 1
t = 52.5 μs
(40% of 125 μs)
Interrupt pending
Microcontroller reads Data 1 in bank 0,
Host sends second data payload
Data OUT 1
Token OUT
Read Bank 2
Write by Hardware
Data OUT 2
Data OUT 2
Cleared by Firmware
Read Bank 3
ACK
t = 125 μs
Token OUT
Read by Microcontroller
Microcontroller reads Data 2 in bank 1,
Host sends third data payload
MDATA0
Interrupt pending
Data OUT 2
RX_BK_RDY
Write in progress
Data OUT 3
Data OUT 3
MDATA1
Read Bank 1
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Cleared by Firmware
USB line
DATA2