ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 816

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

37.7.6
37.7.6.1
816
SAM3U Series
READ_SINGLE_BLOCK Operation using DMA Controller
Block Length is Multiple of 4
7. Wait for XFRDONE in HSMCI_SR register.
1. Wait until the current command execution has successfully completed.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Set RDPROOF bit in HSMCI_MR to avoid overflow.
5. Program HSMCI_DMA register with the following fields:
6. Issue a READ_SINGLE_BLOCK command.
7. Program the DMA controller.
i.
a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
– ROPT field is set to 0.
– OFFSET field is set to 0.
– CHKSIZE is user defined.
– DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMA transfer by
c. Program the channel registers.
d. The DMAC_SADDRx register for channel x must be set with the starting address of
e. The DMAC_DADDRx register for channel x must be word aligned.
f.
g. Program DMAC_CTRLBx register for channel x with the following field’s values:
– DST_INCR is set to INCR.
– SRC_INCR is set to INCR.
– FC field is programmed with peripheral to memory flow control mode.
– both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
– DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
h. Program DMAC_CFGx register for channel x with the following field’s values:
was previously set to false.
DMA controller is able to prefetch data and write HSMCI simultaneously.
for request.
reading the DMAC_EBCISR register.
the HSMCI_FIFO address.
Program DMAC_CTRLAx register of channel x with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4.
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and waiting
HSMCI Host Controller.
6430D–ATARM–25-Mar-11