ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 201

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.20.11.3
• DIVBYZERO
Divide by zero usage fault:
0 = no divide by zero fault, or divide by zero trapping not enabled
1 = the processor has executed an SDIV or UDIV instruction with a divisor of 0.
When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed
the divide by zero.
Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see
on page
• UNALIGNED
Unaligned access usage fault:
0 = no unaligned access fault, or unaligned access trapping not enabled
1 = the processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the CCR to 1, see
Register” on page
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP.
• NOCP
No coprocessor usage fault. The processor does not support coprocessor instructions:
0 = no usage fault caused by attempting to access a coprocessor
1 = the processor has attempted to access a coprocessor.
• INVPC
Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN:
0 = no invalid PC load usage fault
1 = the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid
EXC_RETURN value.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the ille-
gal load of the PC.
• INVSTATE
Invalid state usage fault:
0 = no invalid state usage fault
1 = the processor has attempted to execute an instruction that makes illegal use of the EPSR.
6430D–ATARM–25-Mar-11
15
7
190.
Usage Fault Status Register
190.
14
6
Reserved
The UFSR indicates the cause of a usage fault. The bit assignments are:
13
5
Reserved
12
4
NOCP
11
3
INVPC
10
2
“Configuration and Control Register”
DIVBYZERO
INVSTATE
SAM3U Series
“Configuration and Control
9
1
UNALIGNED
UNDEFINSTR
8
0
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