ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 1073

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

41.6.8
Name:
Address:
Access:
• EOCx: End of Conversion x
0 = Corresponding analog channel is disabled, or the conversion is not finished.
1 = Corresponding analog channel is enabled and conversion is complete.
• OVREx: Overrun Error x
0 = No overrun error on the corresponding channel since the last read of ADC12B_SR.
1 = There has been an overrun error on the corresponding channel since the last read of ADC12B_SR.
• DRDY: Data Ready
0 = No data has been converted since the last read of ADC12B_LCDR.
1 = At least one data has been converted and is available in ADC12B_LCDR.
• GOVRE: General Overrun Error
0 = No General Overrun Error occurred since the last read of ADC12B_SR.
1 = At least one General Overrun Error has occurred since the last read of ADC12B_SR.
• ENDRX: End of RX Buffer
0 = The Receive Counter Register has not reached 0 since the last write in ADC12B_RCR or ADC12B_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in ADC12B_RCR or ADC12B_RNCR.
• RXBUFF: RX Buffer Full
0 = ADC12B_RCR or ADC12B_RNCR have a value other than 0.
1 = Both ADC12B_RCR and ADC12B_RNCR have a value of 0.
6430D–ATARM–25-Mar-11
OVRE7
EOC7
31
23
15
–
–
7
ADC12B Status Register
OVRE6
EOC6
30
22
14
ADC12B_SR
0x400A801C
Read-only
–
–
6
OVRE5
EOC5
29
21
13
–
–
5
OVRE4
EOC4
28
20
12
–
–
4
RXBUFF
OVRE3
EOC3
27
19
11
–
3
ENDRX
OVRE2
EOC2
26
18
10
–
2
SAM3U Series
GOVRE
OVRE1
EOC1
25
17
–
9
1
OVRE0
DRDY
EOC0
24
16
–
8
0
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