ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 930

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

38.7.32
Name:
Address:
Access:
This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.
Only the first 16 bits (channel counter size) of field CV
• CVUPD: Comparison x Value Update
Define the comparison x value to be compared with the counter of the channel 0.
• CVMUPD: Comparison x Value Mode Update
0 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
incrementing.
1 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
decrementing.
Note:
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the register
PWM_CMPMUPDx.
930
930
31
23
15
–
7
This bit is useless if the counter of the channel 0 is left aligned (CALG = 0 in
SAM3U Series
SAM3U Series
PWM Comparison x Value Update Register
PWM_CMPVUPDx
0x4008C134 [0], 0x4008C144 [1], 0x4008C154 [2], 0x4008C164 [3], 0x4008C174 [4], 0x4008C184 [5],
0x4008C194 [6], 0x4008C1A4 [7]
Write-only
30
22
14
–
6
29
21
13
–
5
28
20
12
–
4
UPD
CVUPD
CVUPD
CVUPD
are significant.
27
19
11
–
3
“PWM Channel Mode Register” on page
26
18
10
–
2
25
17
–
9
1
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
CVMUPD
24
16
933)
8
0