ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 187

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.20.6
• VECTKEYSTAT
Register Key:
Reads as 0xFA05
• VECTKEY
Register key:
On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
• ENDIANESS
RO
Data endianness bit:
0 = Little-endian
ENDIANESS is set from the BIGEND configuration signal during reset.
• PRIGROUP
R/W
Interrupt priority grouping field. This field determines the split of group priority from subpriority, see
188.
• SYSRESETREQ
WO
System reset request:
0 = no effect
1 = asserts a proc_reset_signal.
This is intended to force a large system reset of all major components except for debug.
This bit reads as 0.
6430D–ATARM–25-Mar-11
ENDIANESS
31
23
15
7
Application Interrupt and Reset Control Register
30
22
14
6
The AIRCR provides priority grouping control for the exception model, endian status for data
accesses, and reset control of the system. See the register summary in
180
To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the processor
ignores the write.
The bit assignments are:
and
Reserved
Table 13-33 on page 207
29
21
13
5
On Read: VECTKEYSTAT, On Write: VECTKEY
On Read: VECTKEYSTAT, On Write: VECTKEY
Reserved
28
20
12
4
for its attributes.
27
19
11
3
SYSRESETREQ
26
18
10
2
PRIGROUP
VECTCLR-
SAM3U Series
ACTIVE
25
17
9
1
“Binary point” on page
Table 13-30 on page
VECTRESET
24
16
8
0
187