ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 877

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 38-5.
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Period Value
(
Dead-Time Values
(
Duty-Cycle Values
(
Update Period Value
(
PWM_CPRDUPDx)
PWM_DTUPDx)
PWM_CDTYUPDx)
PWM_SCUPUPD)
Summary of the Update of Registers of Synchronous Channels
PWM period as soon as the bit
Update is triggered at the next
• Method 3 (UPDM = 2): same as Method 2 apart from the fact that the duty-cycle values of
Update Period Register”
and automatic trigger of the update” on page
ALL synchronous channels are written by the Peripheral DMA Controller (PDC) (see
3: Automatic write of duty-cycle values and automatic trigger of the update” on page
The user can choose to synchronize the PDC transfer request with a comparison match (see
Section 38.6.3 ”PWM Comparison
register.
UPDULOCK is set to 1
Write by the CPU
Not applicable
Not applicable
UPDM=0
(PWM_SCUP) (see
the bit UPDULOCK is set to 1
the bit UPDULOCK is set to 1
next PWM period as soon as
next PWM period as soon as
Update is triggered at the
Update is triggered at the
Units”), by the fields PTRM and PTRCS in the PWM_SCM
Write by the CPU
Write by the CPU
Write by the CPU
UPDM=1
PWM period as soon as the update period
PWM period as soon as the update period
counter has reached the value UPR
counter has reached the value UPR
“Method 2: Manual write of duty-cycle values
879).
Update is triggered at the next
Update is triggered at the next
Write by the CPU
SAM3U Series
SAM3U Series
Write by the PDC
UPDM=2
“Method
881).
877
877