ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 97

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.10.4
13.10.4.1
6430D–ATARM–25-Mar-11
Shift Operations
ASR
If you omit the shift, or specify LSL #0, the instruction uses the value in Rm.
If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used
by the instruction. However, the contents in the register Rm remains unchanged. Specifying a
register with shift also updates the carry flag when used with certain instructions. For information
on the shift operations and how they affect the carry flag, see
Register shift operations move the bits in a register left or right by a specified number of bits, the
shift length. Register shift can be performed:
The permitted shift lengths depend on the shift type and the instruction, see the individual
instruction description or
occurs. Register shift operations update the carry flag except when the specified shift length is 0.
The following sub-sections describe the various shift operations and how they affect the carry
flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift
length.
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register
into the left-hand n bits of the result. See
You can use the ASR #n operation to divide the value in the register Rm by 2
being rounded towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
Figure 13-4. ASR #3
• directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a
• during the calculation of Operand2 by the instructions that specify the second operand as a
• If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
• If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
destination register
register with shift, see
instruction.
31
LSR #n
ROR #n
RRX
-
logical shift right n bits, 1 ≤ n ≤ 32.
rotate right n bits, 1 ≤ n ≤ 31.
rotate right one bit, with extend.
if omitted, no shift occurs, equivalent to LSL #0.
“Flexible second operand” on page
“Flexible second operand” on page
...
Figure 13-4 on page
96. The result is used by the
“Shift Operations”
96. If the shift length is 0, no shift
97.
5
4
SAM3U Series
3
2
1 0
n
, with the result
Carry
Flag
97