ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 203

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.20.12 Hard Fault Status Register
• DEBUGEVT
Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
• FORCED
Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either
because of priority or because it is disabled:
0 = no forced hard fault
1 = forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault.
• VECTTBL
Indicates a bus fault on a vector table read during exception processing:
0 = no bus fault on vector table read
1 = bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the
exception.
The HFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by writing 1 to that bit, or by a reset.
6430D–ATARM–25-Mar-11
DEBUGEVT
31
23
15
7
FORCED
30
22
14
6
The HFSR gives information about events that activate the hard fault handler. See the register
summary in
This register is read, write to clear. This means that bits in the register read normally, but writing
1 to any bit clears that bit to 0. The bit assignments are:
29
21
13
5
Table 13-30 on page 180
Reserved
28
20
12
4
Reserved
Reserved
for its attributes.
27
19
11
3
Reserved
26
18
10
2
VECTTBL
SAM3U Series
25
17
9
1
Reserved
24
16
8
0
203