ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 433

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.18.21 SMC Mode Register
Name:
Address:
Access:
Reset:
• READ_MODE
1 (NRD_CTRL): The Read operation is controlled by the NRD signal.
0 (NCS_CTRL): The Read operation is controlled by the NCS signal.
• WRITE_MODE
1 (NWE_CTRL): The Write operation is controlled by the NWE signal.
0 (NCS_CTRL): The Write operation is controller by the NCS signal.
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase
Read and Write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro-
grammed for the read and write controlling signal
• BAT: Byte Access Type
This field is used only if DBW defines a 16-bit data bus.
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
• Disabled: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling
cycle is resumed from the point where it was stopped.
read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
31
23
15
–
–
–
7
–
Value
0
1
2
3
0x400E0080 [0], 0x400E0094 [1], 0x400E00A8 [2], 0x400E00BC [3]
0x10000003
SMC_MODEx [x=0..3]
Read-write
30
22
14
–
–
–
6
–
DISABLED
FROZEN
READY
Name
29
21
13
–
–
–
5
EXNW_MODE
Description
Disabled
Reserved
Frozen Mode
Ready Mode
TDF_MODE
DBW
28
20
12
–
4
27
19
11
–
–
3
–
26
18
10
–
–
2
–
TDF_CYCLES
WRITE_MODE READ_MODE
SAM3U Series
SAM3U Series
25
17
–
9
–
1
BAT
24
16
–
8
0
433
433