ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 229

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SAM3U Series
Region
A partition of memory space.
Reserved
A field in a control register or instruction format is reserved if the field is to be defined by the
implementation, or produces Unpredictable results if the contents of the field are not zero. These
fields are reserved for use in future extensions of the architecture or are implementation-specific.
All reserved bits not used by the implementation must be written as 0 and read as 0.
Should Be One (SBO)
Write as 1, or all 1s for bit fields, by software. Writing as 0 produces Unpredictable results.
Should Be Zero (SBZ)
Write as 0, or all 0s for bit fields, by software. Writing as 1 produces Unpredictable results.
Should Be Zero or Preserved (SBZP)
Write as 0, or all 0s for bit fields, by software, or preserved by writing the same value back that
has been previously read from the same field on the same processor.
Thread-safe
In a multi-tasking environment, thread-safe functions use safeguard mechanisms when access-
ing shared resources, to ensure correct operation without the risk of shared access conflicts.
Thumb instruction
One or two halfwords that specify an operation for a processor to perform. Thumb instructions
must be halfword-aligned.
Unaligned
A data item stored at an address that is not divisible by the number of bytes that defines the data
size is said to be unaligned. For example, a word stored at an address that is not divisible by
four.
Undefined
Indicates an instruction that generates an Undefined instruction exception.
Unpredictable (UNP)
You cannot rely on the behavior. Unpredictable behavior must not represent security holes.
Unpredictable behavior must not halt or hang the processor, or any parts of the system.
Warm reset
Also known as a core reset. Initializes the majority of the processor excluding the debug control-
ler and debug logic. This type of reset is useful if you are using the debugging features of a
processor.
Word
A 32-bit data item.
Write
Writes are defined as operations that have the semantics of a store. Writes include the Thumb
instructions STM, STR, STRH, STRB, and PUSH.
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