ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 517

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 30-2.
Notes:
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Offset
0x0070
0x0074
to
0x007C
0x0080
0x0084
0x0088
0x008C
0x0090
to
0x009C
0x00A0
0x00A4
0x00A8
0x00AC
0x00B0
0x00B4
0x00B8
0x00BC
0x00C0
0x00C4
0x00C8
0x00CC
0x00D0
0x00D4
0x00D8
0x00DC
0x00E0
0x00EC
to
0x00F8
0x0100
to
0x0144
0x00E4
0x00E8
1. Reset value of PIO_PSR depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred.
5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register.
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Register
Peripheral AB Select Register
Reserved
System Clock Glitch Input Filter Select Register
Debouncing Input Filter Select Register
Glitch or Debouncing Input Filter Clock Selection Status Register
Slow Clock Divider Debouncing Register
Reserved
Output Write Enable
Output Write Disable
Output Write Status Register
Reserved
Additional Interrupt Modes Enable Register
Additional Interrupt Modes Disables Register
Additional Interrupt Modes Mask Register
Reserved
Edge Select Register
Level Select Register
Edge/Level Status Register
Reserved
Falling Edge/Low Level Select Register
Rising Edge/ High Level Select Register
Fall/Rise - Low/High Status Register
Reserved
Lock Status
Write Protect Mode Register
Write Protect Status Register
Reserved
Reserved
Register Mapping (Continued)
(5)
Name
PIO_ABSR
PIO_SCIFSR
PIO_DIFSR
PIO_IFDGSR
PIO_SCDR
PIO_OWER
PIO_OWDR
PIO_OWSR
PIO_AIMER
PIO_AIMDR
PIO_AIMMR
PIO_ESR
PIO_LSR
PIO_ELSR
PIO_FELLSR
PIO_REHLSR
PIO_FRLHSR
PIO_LOCKSR
PIO_WPMR
PIO_WPSR
Read-Write
Read-Write
Read-write
Write-Only
Write-Only
Read-Only
Write-Only
Write-Only
Read-Only
Write-Only
Write-Only
Read-Only
Write-Only
Write-Only
Read-Only
Read-Only
Read-only
Read-only
Write-only
Write-only
SAM3U Series
SAM3U Series
Access
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
0x0
0x0
–
–
–
–
–
–
–
–
–
–
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