ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 146

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.16.1
13.16.1.1
13.16.1.2
13.16.1.3
146
SAM3U Series
B, BL, BX, and BLX
Syntax
Operation
Restrictions
Branch instructions.
where:
B
BL
BX
BLX
cond
label
Rm
be 1, but the address to branch to is created by changing bit[0] to 0.
All these instructions cause a branch to label, or to the address indicated in Rm. In addition:
Bcond label is the only conditional instruction that can be either inside or outside an IT block. All
other branch instructions must be conditional inside an IT block, and must be unconditional out-
side the IT block, see
Table 13-24
Table 13-24. Branch ranges
You might have to use the .W suffix to get the maximum branch range. See
selection” on page
The restrictions are:
Instruction
B label
Bcond label
Bcond label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
• The BL and BLX instructions write the address of the next instruction to LR (the link register,
• The BX and BLX instructions cause a UsageFault exception if bit[0] of Rm is 0.
R14).
B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
(outside IT block)
(inside IT block)
shows the ranges for the various branch instructions.
is branch (immediate).
is branch with link (immediate).
is branch indirect (register).
is branch indirect with link (register).
is an optional condition code, see
is a PC-relative expression. See
is a register that indicates an address to branch to. Bit[0] of the value in Rm must
102.
“IT” on page
Any value in register
Any value in register
Branch range
− 16 MB to +16 MB
− 1 MB to +1 MB
− 16 MB to +16 MB
− 16 MB to +16 MB
149.
“PC-relative expressions” on page
“Conditional execution” on page
6430D–ATARM–25-Mar-11
“Instruction width
100.
100.