ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 1124

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

43.8
Table 43-38. Channel Conversion Time and ADC Clock
Notes:
Table 43-39. External Voltage Reference Input
43.8.0.3
1124
Parameter
ADC Clock Frequency
ADC Clock Frequency
Startup Time
Track and Hold Acquisition Time
Conversion Time
Throughput Rate
Parameter
ADVREF Input Voltage Range
ADVREF Average Current
Current Consumption on VDDCORE
10-bit Successive Approximation Register (SAR) ADC Characteristics
1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for
2. Corresponds to 15 clock cycles at 8 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for
SAM3U Series
conversion.
conversion
Sample and Hold Time versus Source Output Impedance
Figure 43-11
Figure 43-11. Simplified Acquisition Path
The user can drive ADC input with impedance up to:
with SHTIM (Sample and Hold Time register) expressed in ns and Z
Note:
• Z
• Z
source
source
Csample and Ron are taken into account in the formulas
≤ (SHTIM -470) x 10 in 8-bit resolution mode
≤ (SHTIM -589) x 7.69 in 10-bit resolution mode
gives a simplified acquisition path.
Conditions
13 samples at ADC Clock = 5MHz
Conditions
10-bit resolution mode
8-bit resolution mode
Return from Idle Mode
ADC Clock = 5MHz
ADC Clock = 8MHz
ADC Clock = 5MHz
ADC Clock = 8MHz
Zsource
Input
ADC
Mux.
Ron
Sample & Hold
Csample
Min
2.4
Min
600
0.55
Typ
200
-
source
Typ
ADC
Core
expressed in ohms.
VDDANA+
6430D–ATARM–25-Mar-11
Max
250
384
533
0.2
Max
1.25
1
20
5
8
2
(1)
(2)
Units
kSPS
Units
MHz
MHz
mA
μs
ns
μs
μA
V