ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 776

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

36.6.14.5
776
776
SAM3U Series
SAM3U Series
Speed Measurement
In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on
the TC_CV0 register.
Therefore, the accurate position can be read on both TC_CV registers and concatenated to form
a 32-bit word.
The timer/counter channel 0 is cleared for each increment of IDX count value.
Depending on the quadrature signals, the direction is decoded and allows to count up or down in
timer/counter channels 0 and 1. The direction status is reported on TC_QISR register.
When SPEEDEN is set in TC_BMR register, the speed measure is enabled on channel 0.
A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2
must be configured in waveform mode (WAVE bit field set) in TC_CMR2 register. WAVSEL bit
field must be defined with 0x10 to clear the counter by comparison and matching with TC_RC
value. ACPC field must be defined at 0x11 to toggle TIOA output.
This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are
set.
Channel 0 must be configured in capture mode (WAVE = 0 in TC_CMR0). ABETRG bit field of
TC_CMR0 must be configured at 1 to get TIOA as a trigger for this channel.
EDGTRG can be set to 0x01, to clear the counter on a rising edge of the TIOA signal and LDRA
field must be set accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared
(LDRB must be set to 0x01). As a consequence, at the end of each time base period the differ-
entiation required for the speed calculation is performed.
The process must be started by configuring the TC_CR register with CLKEN and SWTRG.
The speed can be read on TC_RA0 register in TC_CMR0.
Channel 1 can still be used to count the number of revolutions of the motor.
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11