ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 1158

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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SAM3U Series
Comments (Continued)
CORTEX-M3:
Table 13-31, “Priority
Section 13.19.7.1
Section 13.5.2.2 ”Non Maskable Interrupt (NMI)”
Section 13.6.2 ”Fault escalation and hard
Section 13.3.5 ”Data types”
Table 13-11,
Table 13-29, “CMSIS functions for NVIC
on page
Table 13-4, “Memory access
Big Endien not used in this product.
Debug and Test:
Section 14.1
Table 14-1, “Debug and Test Signal
FFPI:
Section 22.2.5.4 ”Flash Lock
HSMCI:
Section 37.12 ”Write Protection
Section 37.13.19 ”HSMCI Write Protect Status
MATRIX:
Table 24-1, “Register
PDC:
Section 26. ”Peripheral DMA Controller (PDC)”
PIO:
Section 30.5.1 ”Write Protection
30.6.43 ”PIO Write Protect Status Register”
PMC:
Section 28.14.16 ”PMC Interrupt Mask
28.14.14 ”PMC Interrupt Disable
Section 28.13 ”Write Protection
Section 28.14.20 ”PMC Write Protect Mode Register”
Section 28.10 ”Clock Failure
Section 28.11 ”Programming
removed code example, bitfield names updated.
PWM:
Table 38-4, “Fault
RSTC:
Section 16.2 ”Block
Section 16.3.1 ”Reset Controller
Section 16.3.4.2 ”Backup
“backup_nreset” replaces “core_backup_reset”.
SMC:
Table 25-4, “External Memory
Section 13.20.6 ”Application Interrupt and Reset Control
55, “...copyright ARM Ltd., 2008 - 2009.” precise years given.
”Overview”, SWJ-DP...also embeds a serial trace.
“Faults,”updated footnote 1
”IP27”, title changed to IP27, value in bitfields 0 to 7 changed to IP28.
Inputs”, “PWM Fault Input Number” column, typos fixed
Diagram”, “backup_nreset” replaces “core_backup_reset”.
grouping,”updated.
Mapping”, added offsets for Write Protection Registers
Reset”, “The vddcore_nreset signal is asserted by the SUPC...” and
Condition tags sorted out.
Detector”, added sentence on Fast RC
Commands”, last sentence removed from 2nd paragraph (ref to EA command).
behavior,”last row assinged to Reserved in Memory Map.
Sequence”, added step 1 and reordered subsequent numbering sequence.
Mapping”, restored rows for chip selects 0, 1, 2 to the table.
Registers”,
Registers”,
Registers”,
Overview”, RSTC_MR...”is powered with VDDBU...”
Register”, 0 and 1read or write values described.
List”, reorganized.
Register”,
control,”Description in 4th row updated.
faults”, last sentence updated with NMI function.
Section 37.13.18 ”HSMCI Write Protect Mode Register”
Section 28.14.20 ”PMC Write Protect Mode Register”
added with links to protected registers.
Section 30.6.42 ”PIO Write Protect Mode Register”
Register”,added.
Section replaced.
added to datasheet.
Section 28.14.13 ”PMC Interrupt Enable
added with links to protected registers.
Register”read/write values to VECTKEY changed
Register”,
and
and
and
Section
Section
6430D–ATARM–25-Mar-11
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