ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 396

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.17 SMC Error Correcting Code Functional Description
25.17.1
25.17.2
396
396
SAM3U Series
SAM3U Series
Write Access
Read Access
A page in NAND Flash and SmartMedia memories contains an area for main data and an addi-
tional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page
size corresponds to the number of words in the main area plus the number of words in the extra
area used for redundancy.
Over time, some memory locations may fail to program or erase properly. In order to ensure that
data is stored properly over the life of the NAND Flash device, NAND Flash providers recom-
mend to utilize either 1 ECC per 256 bytes of data, 1 ECC per 512 bytes of data or 1 ECC for all
of the page.
The only configurations required for ECC are the NAND Flash or the SmartMedia page size
(528/2112/4224) and the type of correction wanted (1 ECC for all the page/1 ECC per 256 bytes
of data /1 ECC per 512 bytes of data). Page size is configured setting the PAGESIZE field in the
ECC Mode Register (ECC_MR). Type of correction is configured setting the TYPCORRECT
field in the ECC Mode Register (ECC_MR).
Note:
ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND
Flash or the SmartMedia is detected. Read and write access must start at a page boundary.
ECC results are available as soon as the counter reaches the end of the main area. Values in
the ECC Parity Registers (ECC_PR0 to ECC_PR15) are then valid and locked until a new start
condition occurs (read/write command followed by address cycles).
Once the Flash memory page is written, the computed ECC codes are available in the ECC Par-
ity (ECC_PR0 to ECC_PR15) registers. The ECC code values must be written by the software
application in the extra area used for redundancy. The number of write accesses in the extra
area is a function of the value of the type of correction field. For example, for 1 ECC per 256
bytes of data for a page of 512 bytes, only the values of ECC_PR0 and ECC_PR1 must be writ-
ten by the software application. Other registers are meaningless.
After reading the whole data in the main area, the application must perform read accesses to the
extra area where ECC code has been previously stored. Error detection is automatically per-
formed by the ECC controller.
Note:
The application can check the ECC Status Registers (ECC_SR1/ECC_SR2) for any detected
errors. It is up to the application to correct any detected error. ECC computation can detect four
different circumstances:
• No error: XOR between the ECC computation and the ECC code stored at the end of the
• Recoverable error: Only the RECERR flags in the ECC Status registers
NAND Flash or SmartMedia page is equal to 0. No error flags in the ECC Status Registers
(ECC_SR1/ECC_SR2).
(ECC_SR1/ECC_SR2) are set. The corrupted word offset in the read page is defined by the
WORDADDR field in the ECC Parity Registers (ECC_PR0 to ECC_PR15). The corrupted bit
position in the concerned word is defined in the BITADDR field in the ECC Parity Registers
(ECC_PR0 to ECC_PR15).
There is a limitation when using a 16-bit NAND Flash: only 1 ECC for a whole page is possible.
There is no limitation when using an 8-bit NAND Flash.
It is mandatory to read consecutively the entire main area and the locations where Parity and
NParity values have been previously stored, to let the ECC controller perform error detection.
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11