ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 181

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.20.2
• DISFOLD
When set to 1, disables IT folding. see
• DISDEFWBUF
When set to 1, disables write buffer use during default memory map accesses. This causes all bus faults to be precise bus
faults but decreases performance because any store to memory must complete before the processor can execute the next
instruction.
This bit only affects write buffers implemented in the Cortex-M3 processor.
• DISMCYCINT
When set to 1, disables interruption of load multiple and store multiple instructions. This increases the interrupt latency of
the processor because any LDM or STM must complete before the processor can stack the current state and enter the
interrupt handler.
13.20.2.1
6430D–ATARM–25-Mar-11
31
23
15
7
Auxiliary Control Register
About IT folding
30
22
14
6
The ACTLR provides disable bits for the following processor functions:
See the register summary in
ments are:
In some situations, the processor can start executing the first instruction in an IT block while it is
still executing the IT instruction. This behavior is called IT folding, and improves performance,
However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit to
1 before executing the task, to disable IT folding.
• IT folding
• write buffer use for accesses to the default memory map
• interruption of multi-cycle instructions.
Reserved
29
21
13
5
“About IT folding” on page 181
28
20
12
4
Table 13-30 on page 180
Reserved
Reserved
Reserved
27
19
11
3
for more information.
DISFOLD
for the ACTLR attributes. The bit assign-
26
18
10
2
DISDEFWBUF
SAM3U Series
25
17
9
1
DISMCYCINT
24
16
8
0
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