ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 810

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

37.7.2
37.7.3
810
SAM3U Series
Data Transfer Operation
Read Operation
The High Speed MultiMedia Card allows several read/write operations (single block, multiple
blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP)
field in the HSMCI Command Register (HSMCI_CMDR).
These operations can be done using the features of the DMA Controller.
In all cases, the block length (BLKLEN field) must be defined either in the mode register
HSMCI_MR, or in the Block Register HSMCI_BLKR. This field determines the size of the data
block.
Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions
are defined (the host can use either one at any time):
The following flowchart
DMAC facilities. In this example, a polling method is used to wait for the end of read. Similarly,
the user can configure the interrupt enable register (HSMCI_IER) to trigger an interrupt at the
end of read.
• Open-ended/Infinite Multiple block read (or write):
• Multiple block read (or write) with pre-defined block count (since version 3.1 and higher):
The number of blocks for the read (or write) multiple block operation is not defined. The card
will continuously transfer (or program) data blocks until a stop transmission command is
received.
The card will transfer (or program) the requested number of data blocks and terminate the
transaction. The stop command is not required at the end of this type of multiple block read
(or write), unless terminated with an error. In order to start a multiple block read (or write)
with pre-defined block count, the host must correctly program the HSMCI Block Register
(HSMCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT
field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks).
Programming the value 0 in the BCNT field corresponds to an infinite block transfer.
(Figure
37-8) shows how to read a single block with or without use of
6430D–ATARM–25-Mar-11