ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 630

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

33.7.7
33.7.7.1
33.7.7.2
33.7.8
Figure 33-14. SMBUS Quick Command
33.7.9
630
SAM3U Series
Using the Peripheral DMA Controller (PDC)
SMBUS Quick Command (Master Mode Only)
Read-write Flowcharts
Data Transmit with the PDC
Data Receive with the PDC
The use of the PDC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequences:
The TWI interface can perform a Quick Command:
The following flowcharts shown in
33-18 on page
read and write operations. A polling or interrupt method can be used to check the status bits.
The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
1. Initialize the transmit PDC (memory pointers, size, etc.).
2. Configure the master mode (DADR, CKDIV, etc.).
3. Start the transfer by setting the PDC TXTEN bit.
4. Wait for the PDC end TX flag.
5. Disable the PDC by setting the PDC TXDIS bit.
1. Initialize the receive PDC (memory pointers, size - 1, etc.).
2. Configure the master mode (DADR, CKDIV, etc.).
3. Start the transfer by setting the PDC RXTEN bit.
4. Wait for the PDC end RX flag.
5. Disable the PDC by setting the PDC RXDIS bit.
1. Configure the master mode (DADR, CKDIV, etc.).
2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to
3. Start the transfer by setting the QUICK bit in the TWI_CR.
be sent.
TXCOMP
Write QUICK command in TWI_CR
TXRDY
634,
TWD
Figure 33-19 on page 635
S
DADR
Figure 33-16 on page
R/W
and
A
Figure 33-20 on page 636
P
632,
Figure 33-17 on page
6430D–ATARM–25-Mar-11
give examples for
633,
Figure