ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 215

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.22.2
• PRIVDEFENA
Enables privileged software access to the default memory map:
0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any
enabled region causes a fault.
1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software
accesses.
When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority
over this default map.
If the MPU is disabled, the processor ignores this bit.
• HFNMIENA
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0 = MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit
1 = the MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1 the behavior is Unpredictable.
• ENABLE
Enables the MPU:
0 = MPU disabled
1 = MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
For privileged accesses, the default memory map is as described in
software that does not address an enabled memory region behaves as defined by the default memory map.
6430D–ATARM–25-Mar-11
31
23
15
7
MPU Control Register
30
22
14
6
The MPU CTRL register:
See the register summary in
assignments are:
• enables the MPU
• enables the default memory map background region
• enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and
FAULTMASK escalated handlers.
Reserved
29
21
13
5
28
20
12
4
Table 13-35 on page 213
Reserved
Reserved
Reserved
27
19
11
“Memory model” on page
3
PRIVDEFENA
26
18
10
2
for the MPU CTRL attributes. The bit
70. Any access by privileged
HFNMIENA
SAM3U Series
25
17
9
1
ENABLE
24
16
8
0
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