ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 1060

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

41.5.6
41.5.7
Figure 41-3. EOCx and DRDY Flag Behavior
1060
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
EOCx
DRDY
CHx
SAM3U Series
Power Consumption Adjustment
Conversion Results
Write the ADC_CR
with START = 1
The power consumption of the ADC12B can be adjusted through a 2-bit bias control (IBCTL bit
in ADC12B_ACR register) providing possibilities for smart optimization of power and effective
resolution relative to the application speed request.
Please refer to the Electrical Characteristics of the product datasheet for further details.
When a conversion is completed, the resulting 12-bit digital value is stored in the Channel Data
Register (ADC12B_CDR) of the current channel and in the ADC12B Last Converted Data Regis-
ter (ADC12B_LCDR).
The channel EOC bit in the Status Register (ADC12B_SR) is set and the DRDY bit is set. In the
case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case,
either EOC and DRDY can trigger an interrupt.
Reading one of the ADC12B_CDR registers clears the corresponding EOC bit. Reading
ADC12B_LCDR clears the DRDY bit and the EOC bit corresponding to the last converted
channel.
Conversion Time
Read the ADC_CDRx
Write the ADC_CR
with START = 1
Conversion Time
Read the ADC_LCDR
6430D–ATARM–25-Mar-11