ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 698

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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SAM3U Series
SAM3U Series
mat is modified and includes sync information.
sists of a user-defined pattern that indicates the beginning of a valid data.
illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT
to 1), a logic zero is Manchester encoded and indicates that a new character is being sent seri-
ally on the line. If the start frame delimiter is a synchronization pattern also referred to as sync
(ONEBIT to 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new
character. The sync waveform is in itself an invalid Manchester waveform as the transition
occurs at the middle of the second bit time. Two distinct sync patterns are used: the command
sync and the data sync. The command sync has a logic one level for one and a half bit times,
then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in
the US_MR register is set to 1, the next character is a command. If it is set to 0, the next charac-
ter is a data. When direct memory access is used, the MODSYNC field can be immediately
updated with a modified character located in memory. To enable this mode, VAR_SYNC field in
US_MR register must be set to 1. In this case, the MODSYNC field in US_MR is bypassed and
the sync configuration is held in the TXSYNH in the US_THR register. The USART character for-
Figure 35-9. Preamble Patterns, Default Polarity Assumed
A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It con-
Manchester
Manchester
Manchester
Manchester
encoded
encoded
encoded
encoded
data
data
data
data
Txd
Txd
Txd
Txd
8 bit width "ZERO_ONE" Preamble
8 bit width "ONE_ZERO" Preamble
8 bit width "ALL_ZERO" Preamble
8 bit width "ALL_ONE" Preamble
SFD
SFD
SFD
SFD
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Figure 35-10
DATA
DATA
DATA
DATA