ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 1134

IC MCU 32BIT 256KB FLSH 100TFBGA

ATSAM3U4CA-CU

Manufacturer Part Number
ATSAM3U4CA-CU
Description
IC MCU 32BIT 256KB FLSH 100TFBGA
Manufacturer
Atmel
Series
SAM3Ur
Datasheets

Specifications of ATSAM3U4CA-CU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
52K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
52 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3U4CA-CU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATSAM3U4CA-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
43.9.6
43.9.6.1
Table 43-48. SMC Read Signals - NRD Controlled (READ_MODE = 1)
1134
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
1
2
3
4
5
6
7
SAM3U Series
SMC Timings
Read Timings
Parameter
Data Setup before NRD High
Data Hold after NRD High
Data Setup before NRD High
Data Hold after NRD High
A2 - A25 Valid before NRD High
NCS low before NRD High
NRD Pulse Width
NBS0/A0, NBS1, NBS2/A1, NBS3,
VDDIO Supply
Figure 43-24. Min and Max Access Time of Output Signals
SMC Timings are given with the following conditions.
VDDIO = 1.62V @ 30 pF
VDDIO = 3V @ 50 pF
Timings are given assuming a capacitance load on data, control and address pads:
In the following tables t
HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold = 0)
NO HOLD SETTINGS (nrd hold = 0)
TK (CKI =0)
TK (CKI =1)
HOLD SETTINGS (nrd hold ≠ 0)
nrd pulse - ncs
TF/TD
CPMCK
(nrd setup +
(nrd setup +
nrd pulse)*
nrd pulse *
rd setup) *
t
t
t
CPMCK
CPMCK
CPMCK
1.8V
17.5
17
0
0
is MCK period. Timing extraction
(2)
+ 7
+ 8
- 5
Min
nrd pulse - ncs
(nrd setup +
t
(nrd setup +
nrd pulse)*
CPMCK
nrd pulse *
rd setup) *
t
t
CPMCK
CPMCK
3.3V
SSC
16
15
SSC
0
0
+ 6.5
(3)
0max
+ 7
0min
- 5
1.8V
(2)
Max
3.3V
6430D–ATARM–25-Mar-11
(3)
Units
ns
ns
ns
ns
ns
ns
ns

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