ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 890

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

38.6.5.4
890
890
SAM3U Series
SAM3U Series
Changing the Synchronous Channels Update Period
It is possible to change the update period of synchronous channels while they are enabled. (See
“Method 2: Manual write of duty-cycle values and automatic trigger of the update” on page 879
and
page
To prevent an unexpected update of the synchronous channels registers, the user must use the
“PWM Sync Channels Update Period Update Register”
update period of synchronous channels while they are still enabled. This register holds the new
value until the end of the update period of synchronous channels (when UPRCNT is equal to
UPR in
rent PWM period, then updates the value for the next period.
Note:
Note:
Figure 38-17. Synchronized Update of Update Period Value of Synchronous Channels
“Method 3: Automatic write of duty-cycle values and automatic trigger of the update” on
881.)
“PWM Sync Channels Update Period Register”
If the update register PWM_SCUPUPD is written several times between two updates, only the last
written value is taken into account.
Changing the update period does make sense only if there is one or more synchronous channels
and if the update method 1 or 2 is selected (UPDM = 1 or 2 in
Register”).
End of PWM period and
end of Update Period
of Synchronous Channels
PWM_SCUPUPD Value
User's Writing
PWM_SCUP
(PWM_SCUP)) and the end of the cur-
(PWM_SCUPUPD) to change the
“PWM Sync Channels Mode
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11