ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 938

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

38.7.39
Name:
Address:
Access:
This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in
page
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the
waveform period.
Only the first 16 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
938
938
928.
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
31
23
15
–
7
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
64, 128, 256, 512, or 1024). The resulting period formula will be:
(
------------------------------------------------------- -
respectively:
(
------------------------------------------------------------------ -
(
---------------------------------------------
2
2
X
(
-------------------------------------------------------- -
CRPDUPD
SAM3U Series
SAM3U Series
×
×
×
PWM Channel Period Update Register
X
CPRDUPD
CPRDUPD
MCK
×
PWM_CPRDUPDx [x=0..3]
0x4008C210 [0], 0x4008C230 [1], 0x4008C250 [2], 0x4008C270 [3]
Write-only
MCK
CPRDUPD
MCK
MCK
×
30
22
14
DIVA
–
6
)
×
DIVA
)
)
or
)
or
(
-------------------------------------------------------- -
CRPDUPD
(
------------------------------------------------------------------ -
2
×
29
21
13
–
5
CPRDUPD
MCK
MCK
×
DIVB
×
)
DIVB
28
20
12
–
4
CPRDUPD
CPRDUPD
CPRDUPD
)
27
19
11
–
3
“PWM Write Protect Status Register” on
26
18
10
–
2
25
17
–
9
1
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
24
16
–
8
0