ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 342

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.4.3
24.5
342
Write Protect Registers
SAM3U Series
Fixed Priority Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave by using the fixed priority defined by the user. If two or more master’s requests
are active at the same time, the master with the highest priority number is serviced first. If two or
more master’s requests with the same priority are active at the same time, the master with the
highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for
Slaves (MATRIX_PRAS and MATRIX_PRBS).
To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX
address space from address offset 0x000 to 0x1FC can be write-protected by setting the WPEN
bit in the MATRIX Write Protect Mode Register (MATRIX_WPMR).
If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC
is detected, then the WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR)
is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR)
with the appropriate access key WPKEY.
The protected registers are:
“Bus Matrix Master Configuration Registers”
“Bus Matrix Slave Configuration Registers”
“Bus Matrix Priority Registers For Slaves”
“Bus Matrix Master Remap Control Register”
“Bus Matrix Master Remap Control Register”
6430D–ATARM–25-Mar-11