ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 506

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

30.5
Figure 30-3. I/O Line Control Logic
506
506
PIO_SCDR
Functional Description
SAM3U Series
SAM3U Series
Slow Clock
System Clock
Output Enable
Output Enable
Peripheral A
Peripheral B
Peripheral A
Peripheral B
Output
Output
PIO_SCIFSR[0]
PIO_DCIFSR[0]
PIO_IFSCR[0]
Divider
Clock
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic asso-
ciated to each I/O is represented in
represents but one of up to 32 possible indexes.
PIO_ABSR[0]
1
0
PIO_IFER[0]
PIO_IFDR[0]
Programmable
PIO_OER[0]
PIO_ODR[0]
Debouncing
PIO_IFSR[0]
1
1
Glitch
0
0
Filter
or
PIO_OSR[0]
PIO_SODR[0]
PIO_CODR[0]
PIO_PER[0]
PIO_PDR[0]
1
0
PIO_ODSR[0]
PIO_PSR[0]
Resynchronization
D
DFF
Q
Stage
D
PIO_PDSR[0]
DFF
Q
Figure
1
0
1
0
PIO_MDER[0]
PIO_MDDR[0]
30-3. In this description each signal shown
DETECTOR
PIO_IDR[31]
PIO_IER[31]
EVENT
PIO_MDSR[0]
PIO_IDR[0]
PIO_IER[0]
PIO_IMR[31]
PIO_ISR[31]
PIO_IMR[0]
1
0
0
1
PIO_PUER[0]
PIO_PUDR[0]
PIO_ISR[0]
PIO_PUSR[0]
(Up to 32 possible inputs)
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Peripheral A
Peripheral B
PIO Interrupt
Input
Input
Pad