ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 381

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.15 Slow Clock Mode
25.15.1
Figure 25-28. Read/Write Cycles in Slow Clock Mode
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
NBS0, NBS1,
Slow Clock Mode Waveforms
A[23:2]
A0,A1
NWE
MCK
NCS
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the Power Management Controller is asserted because MCK has
been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-pro-
grammed waveforms are ignored and the slow clock mode waveforms are applied. This mode is
provided so as to avoid reprogramming the User Interface with appropriate waveforms at very
slow clock rate. When activated, the slow mode is active on all chip selects.
Figure 25-28
chip selects.
Table 25-8.
SLOW CLOCK MODE WRITE
1
Read Parameters
NRD_SETUP
NRD_PULSE
NCS_RD_SETUP
NCS_RD_PULSE
NRD_CYCLE
NWE_CYCLE = 3
1
Table 25-8
illustrates the read and write operations in slow clock mode. They are valid on all
Read and Write Timing Parameters in Slow Clock Mode
1
indicates the value of read and write parameters in slow clock mode.
Duration (cycles)
1
1
0
2
2
NBS0, NBS1,
Write Parameters
NWE_SETUP
NWE_PULSE
NCS_WR_SETUP
NCS_WR_PULSE
NWE_CYCLE
A[23:2]
A0,A1
MCK
NRD
NCS
SLOW CLOCK MODE READ
NRD_CYCLE = 2
1
SAM3U Series
SAM3U Series
Duration (cycles)
1
1
1
0
3
3
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