ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 710

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

35.7.3.12
35.7.3.13
710
710
SAM3U Series
SAM3U Series
Framing Error
Transmit Break
Table 35-11. Maximum Time-out Period (Continued)
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of
a received character is detected at level 0. This can occur if the receiver and the transmitter are
fully desynchronized.
A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The
FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is
cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1.
Figure 35-25. Framing Error Status
The user can request the transmitter to generate a break condition on the TXD line. A break con-
dition drives the TXD line low during at least one complete character. It appears the same as a
0x00 character sent with the parity and the stop bits to 0. However, the transmitter holds the
TXD line at least during one character until the user requests the break condition to be removed.
A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit to 1. This
can be performed at any time, either while the transmitter is empty (no character in either the
Shift Register or in US_THR) or when a character is being transmitted. If a break is requested
while a character is being shifted out, the character is first completed before the TXD line is held
low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of
the break is completed.
The break condition is removed by writing US_CR with the STPBRK bit to 1. If the STPBRK is
requested before the end of the minimum break duration (one character, including start, data,
parity and stop bits), the transmitter ensures that the break condition completes.
Baud Rate
Baud Rate
200000
56000
57600
FRAME
RXRDY
US_CR
Clock
Write
RXD
Start
Bit
D0
D1
D2
D3
D4
Bit Time
D5
18
17
5
D6
D7
Parity
Bit
Stop
Bit
RSTSTA = 1
Time-out
1 170
1 138
328
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11