ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 888

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

38.6.5.2
38.6.5.3
888
888
SAM3U Series
SAM3U Series
Source Clock Selection Criteria
Changing the Duty-Cycle, the Period and the Dead-Times
The large number of source clocks can make selection difficult. The relationship between the
value in the
Cycle Register”
Period Register gives the PWM accuracy. The Duty-Cycle quantum cannot be lower than
1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value
from between 1 up to 14 in PWM_CDTYx Register. The resulting duty-cycle quantum cannot be
lower than 1/15 of the PWM period.
It is possible to modulate the output waveform duty-cycle, period and dead-times.
To prevent unexpected output waveform, the user must use the
Update
Time Update Register”
waveform parameters while the channel is still enabled.
Note:
• If the channel is an asynchronous channel (SYNCx = 0 in
• If the channel is a synchronous channel and update method 0 is selected (SYNCx = 1 and
• If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx=1 and
Register”
values until the end of the current PWM period and update the values for the next period.
UPDM = 0 in PWM_SCM register), these registers hold the new period, duty-cycle and dead-
times values until the bit UPDULOCK is written at “1” (in
Control Register”
values for the next period.
UPDM=1 or 2 in PWM_SCM register):
– registers PWM_CPRDUPDx and PWM_DTUPDx hold the new period and dead-
– register PWM_CDTYUPDx holds the new duty-cycle value until the end of the
times values until the bit UPDULOCK is written at “1” (in PWM_SCUC register) and
the end of the current PWM period, then update the values for the next period.
update period of synchronous channels (when UPRCNT is equal to UPR in
Sync Channels Update Period Register”
PWM period, then updates the value for the next period.
Register”, the
If the update registers PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx are written
several times between two updates, only the last written value is taken into account.
(PWM_SCM)), these registers hold the new period, duty-cycle and dead-times
“PWM Channel Period Register”
(PWM_CDTYx) can help the user in choosing. The event number written in the
(PWM_SCUC)) and the end of the current PWM period, then update the
“PWM Channel Period Update Register”
(PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx) to change
(PWM_CPRDx) and the
(PWM_SCUP)) and the end of the current
“PWM Sync Channels Update
“PWM Sync Channels Mode
and the
“PWM Channel Duty Cycle
“PWM Channel Dead
“PWM Channel Duty
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
“PWM