ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 642

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 33-25. Read Access Ordered by a MASTER
Notes:
33.9.5.2
Figure 33-26. Write Access Ordered by a Master
Notes:
642
EOSVACC
EOSVACC
SVREAD
SVREAD
SVACC
RXRDY
TXRDY
SVACC
NACK
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read.
TWD
TWD
SAM3U Series
acknowledged or non acknowledged.
Write Operation
S
S
ADR
ADR
TWI answers with a NACK
TWI answers with a NACK
SADR does not match,
SADR does not match,
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address
is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in
this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the
TWI_RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 33-26 on page 642
W
R
NA
NA
DATA
DATA
NA
NA
P/S/Sr
P/S/Sr
describes the Write operation.
Write THR
SADR
SADR
TWI answers with an ACK
TWI answers with an ACK
SADR matches,
SADR matches,
W A
R
SVREAD has to be taken into account only while SVACC is active
SVREAD has to be taken into account only while SVACC is active
A
DATA
DATA
A
A
Read RHR
ACK/NACK from the Master
A
A
DATA NA S/Sr
DATA
NA
6430D–ATARM–25-Mar-11
S/Sr
Read RHR