ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 1165

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24 Bus Matrix (MATRIX) ............................................................................ 339
25 Static Memory Controller (SMC) ......................................................... 353
26 Peripheral DMA Controller (PDC) ....................................................... 441
27 Clock Generator ................................................................................... 453
6430D–ATARM–25-Mar-11
23.5 Hardware and Software Constraints ..................................................................338
24.1 Description .........................................................................................................339
24.2 Memory Mapping ...............................................................................................339
24.3 Special Bus Granting Techniques .....................................................................339
24.4 Arbitration ..........................................................................................................340
24.5 Write Protect Registers ......................................................................................342
24.6 Bus Matrix (MATRIX) User Interface .................................................................343
25.1 Description .........................................................................................................353
25.2 Embedded Characteristics ................................................................................353
25.3 Block Diagram ...................................................................................................354
25.4 I/O Lines Description .........................................................................................355
25.5 Multiplexed Signals ............................................................................................355
25.6 Application Example ..........................................................................................356
25.7 Product Dependencies ......................................................................................356
25.8 External Memory Mapping .................................................................................357
25.9 Connection to External Devices ........................................................................358
25.10 Standard Read and Write Protocols ................................................................360
25.11 Scrambling/Unscrambling Function .................................................................366
25.12 Automatic Wait States .....................................................................................367
25.13 Data Float Wait States .....................................................................................370
25.14 External Wait ...................................................................................................375
25.15 Slow Clock Mode .............................................................................................381
25.16 NAND Flash Controller Operations .................................................................384
25.17 SMC Error Correcting Code Functional Description ........................................396
25.18 Static Memory Controller (SMC) User Interface ..............................................400
26.1 Description .........................................................................................................441
26.2 Block Diagram ...................................................................................................442
26.3 Functional Description .......................................................................................442
26.4 Peripheral DMA Controller (PDC) User Interface ..............................................445
27.1 Description .........................................................................................................453
27.2 Block Diagram ...................................................................................................454
SAM3U Series
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